Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable test benches from scratch.
2. Develop functional coverage models and close code coverage.
3. Utilize UVM to create drivers, monitors, predictors, and scoreboards.
4. Integrate with HW/software supporting lab integration and complete testing/qualification of a deliverable system.
• Thorough understanding of FPGA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test.
• Ability to Work independently to develop test bench solutions.
Job ID: 16597